This invention relates to the measurement of gate delays in integrated circuit wafers. More particularly, this invention relates to apparatus and a method for measuring the gate delay in an integrated circuit wafer, which apparatus does not need as wide a bandwidth as previously known testing apparatus.
Variations in the manufacturing process for integrated circuit wafers sometimes occur, giving rise to variations in wafer characteristic from batch to batch of wafers, or even from wafer to wafer within a given batch. It is important that these various characteristics all meet certain specifications, or at least that their values be known.
One such characteristic is the gate delay. A common method of measuring gate delay is to include a ring oscillator circuit on the wafer. This circuit is a chain of an odd number of inverters, with the output of the last inverter connected to the input of the first inverter. When the input of the first inverter is made high, the circuit begins to oscillate, with the output changing from high to low as a square wave, which can be observed by placing probes of an appropriate testing apparatus on appropriate pads of the wafer. The width of each high or low portion of the square wave is equal to the total delay of the circuit, which in turn is equal to the product of the number of inverters and the average individual delay of each inverter (the individual delay is approximately the same for each inverter on a given wafer). Thus the period of the square wave is equal to twice that product.
A typical gate delay is between about 0.2 nsec and 1.0 nsec. The number of inverters used in a typical ring oscillator circuit is usually 11, 13 or 29. Thus the period of the square wave can be as short as about 4.4 nsec. Accordingly, the testing apparatus must have a bandwidth of up to about 227 MHz to be able to resolve the square wave output of the ring oscillator.
In addition, test procedures using a ring oscillator are not compatible with automated testing equipment, because the ring oscillator is free-running, and therefore difficult to synchronize with the test equipment. Accordingly, a human operator must read the oscillation period from an oscilloscope and calculate the gate delay manually or, at best, enter the period into the automated testing equipment which then calculates the gate delay.
It would be desirable to be able to provide apparatus and a method for testing the gate delay in an integrated circuit wafer, the apparatus not needing a high bandwidth.
It would also be desirable to be able to provide such apparatus and method which are compatible with automated testing equipment and methods.